Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer

Intel has revealed a new high-bandwidth memory (HBM) architecture, called Cross-Batch Memory (XBM), in a patent filed in December 2024 and published in July 2026. XBM aims to overcome the high packagi... Read original →

Intel’s XBM architecture fundamentally redefines HBM by shifting DRAM integration to BEOL with thin-film transistors and replacing wide parallel buses with a 32 GT/s UCIe serial link. This move directly undermines the economics of silicon interposers, eroding TSMC’s CoWoS dominance and pressuring SK Hynix and Micron to accelerate non-TSV DRAM alternatives. From a compliance standpoint, reduced reliance on advanced lithography and TSVs eases exposure to U.S. export controls on advanced packaging materials, enhancing supply chain flexibility across Taiwan, China and Southeast Asia. NVIDIA may be forced to fast-track co-packaged optics with chiplet-native memory, while AMD could partner with IP firms like SAIMEMORY to close the gap. Within 18 months, successful integration of XBM with Intel’s ZAM could slash AI memory bandwidth costs by over 30% and catalyze a new 'interposer-less' HBM standard—reshaping the entire high-bandwidth memory ecosystem.