Imec advances platform for integrating III‑V chiplets with Si‑CMOS - New Electronics

Imec's advancement in III-V chiplet integration with Si-CMOS represents a significant breakthrough in semiconductor technology, addressing long-standing challenges in hetero-integration. The platform ... Read original →

Imec’s breakthrough in III-V/Si-CMOS heterogeneous integration will force a redesign of RF front-ends, AI accelerators, and mmWave chips. Technically, it pressures ASML and Applied Materials to tailor EUV and hybrid bonding tools for compound semiconductors. Geopolitically, reliance on U.S.-origin equipment or EDA could raise adoption barriers for non-U.S. foundries like SMIC or UMC under tightening export controls. TSMC, already advancing SoIC and InFO-RDL, will likely accelerate its III-V roadmap to defend its lead, while Intel may leverage Foveros for a countermove. Within 12–24 months, pilot production on 200mm wafers will spur demand for GaAs/GaN epitaxial substrates and push UCIe to standardize III-V chiplet interfaces—triggering a new battle for ecosystem dominance.