Chiplets Need A New Workflow - Semiconductor Engineering

As the semiconductor industry transitions from planar SoCs to multi-die chiplet systems, the complexity of chip design has significantly increased. Chiplets not only alter chip architecture but also f... Read original →

The chiplet shift is triggering a foundational redesign of semiconductor workflows. Technically, EDA must evolve from monolithic simulation to multi-physics co-analysis—thermal-mechanical-electrical coupling can no longer be an afterthought, as hybrid bonding at 3nm tolerates zero micro-strain without catastrophic yield loss. Compliance-wise, while UCIe lowers interoperability barriers, it heightens IP validation risks amid U.S.-EU localization mandates, forcing firms to diversify supply chains. Strategically, TSMC leverages CoWoS dominance to lock in NVIDIA, while Synopsys and Siemens EDA race to embed AI into chiplet-aware verification platforms to control the design entry point. Within 18 months, smaller IP vendors lacking system-level design capabilities will be squeezed out; advanced packaging access and multi-physics simulation prowess will define the new competitive moat.