Cadence and Samsung Foundry enable 2nd gen 2nm - Electronics Weekly

Cadence and Samsung Foundry have collaborated to advance the second-generation 2nm process, expanding Cadence's IP portfolio and enabling next-generation AI infrastructure and system designs. The init... Read original →

Samsung Foundry’s deep integration with Cadence on its second-gen 2nm node is less a process upgrade and more a strategic grab for AI chip ecosystem control. Technically, the 3D Cube-H hybrid copper bonding forces a full-stack EDA rearchitecture—especially raising signal integrity barriers for HBM4 and UCIe, effectively pricing out smaller design houses. On compliance, tightening U.S.-led export controls on lithography tools heighten Samsung’s risk of yield ramp delays if it reduces reliance on U.S. EDA, jeopardizing commitments to NVIDIA or Google. In response, TSMC will likely accelerate its A16 (1.6nm) and SoIC-X co-integration with Synopsys to counter Samsung’s SerDes and NVLink-C2C edge. Over the next 18 months, this rivalry will accelerate chiplet standardization—but the real winners will be EDA vendors commanding high-speed interface IP and thermo-electrical signoff capabilities. Cadence is positioning itself as the gatekeeper of AI infrastructure’s foundational layer.