Cadence and Samsung Foundry deepen 2nm and 3D‑IC collaboration to meet surging AI infrastructure and physical AI demand - Manila Standard

Cadence and Samsung Foundry have deepened their collaboration on 2nm and 3D IC technologies to address the surging demand for AI infrastructure and physical AI. This multi-year agreement expands the p... Read original →

Samsung Foundry’s intensified alliance with Cadence on 2nm and 3D-IC isn’t just process scaling—it’s a strategic bet on AI’s physical limits. Technically, this accelerates convergence of EUV layering, hybrid copper bonding (HCB), and chiplet interconnects like NVLink-C2C and UCIe, forcing EDA flows to shift from single-die signoff to full-system co-simulation—directly challenging TSMC’s CoWoS dominance. Compliance-wise, U.S.-led export controls on lithography tools have inflated 2nm yield ramp costs by over 30%; if Samsung misses HBM4-integrated 2nm volume by late 2027, its AI foundry share risks collapse. Synopsys will counter by deepening Intel 18A integration and pushing DSO.ai as the design gateway. Over the next 18 months, 2nm becomes the AI chip ‘entry ticket,’ but victory hinges on thermal-electrical-mechanical signoff in 3D stacks—the very moat Cadence’s Integrity 3D-IC platform defends.