Cadence and Samsung expand partnership for advanced chip design at 2nm - New Electronics

Cadence Design Systems and Samsung Foundry have expanded their partnership to focus on advanced chip design tools and intellectual property (IP) for next-generation semiconductors, particularly those ... Read original →

Samsung and Cadence’s 2nm alliance is a strategic pivot toward system-level innovation as AI chips hit physical scaling limits. Technically, it accelerates 3D-IC and chiplet adoption by standardizing high-bandwidth interconnects like NVLink-C2C and UCIe, forcing EDA flows to evolve from monolithic to multi-die co-design. Geopolitically, tightened U.S.-Dutch export controls on High-NA EUV tools threaten Samsung’s 2nm ramp, potentially inflating Cadence’s IP validation costs. In response, TSMC may counter with deeper Synopsys integration around SoIC-X, while SMIC’s IP ecosystem gaps above 28nm will widen. Over the next 18 months, this partnership will shift AI accelerator design from process-centric to architecture-centric—but if EDA decoupling risks escalate, Chinese firms may fast-track domestic alternatives, inadvertently accelerating homegrown EDA trials in advanced packaging.