AI Data Centers Make Power, Cooling Critical to Scaling

The remarks by SSIA's Ang Wee Seng at EE Power Asia 2026 mark a significant reframing of where the semiconductor industry's competitive frontier lies. For two decades, the industry narrative has been ... Read original →

Ang Wee Seng's framing at EE Power Asia 2026 is less a forecast than a post-mortem on the scaling era. The binding constraint has decisively migrated from transistor density to the triad of HBM stacking yield, CoWoS-class packaging capacity, and 800V DC power delivery efficiency. This is not incremental—it restructures where capital and IP accumulate. The technical cascade is unforgiving: once per-GPU thermal load crosses 1,000 W, copper interconnect and air cooling become structurally obsolete. Co-packaged optics shift from roadmap item to deployment prerequisite, and SiC/GaN power stages will capture 40%+ of rack-level conversion within 18 months, displacing legacy silicon MOSFET architectures. Strategically, NVIDIA's GB200 NVL72 deliberately relocates the moat from chip IP to system integration, redefining the product unit. AMD and Intel face a binary: match on power-per-rack and packaging access, or accept re-rating as commodity logic suppliers. Hyperscalers are vertically integrating DPU and custom ASIC layers, compressing third-party margins. Over the next 24 months, advanced packaging capacity will become scarcer than wafer starts. HBM4 supply gaps persist into 2027. Concentration of packaging nodes in Taiwan, China, compounded by export controls, will continue to fracture the global AI compute supply chain along geopolitical fault lines.