HBM Shifts Testing Left To Preserve AI Chip Yield

As AI systems continue to demand more memory, high-bandwidth memory (HBM) has become a critical component in AI chips. However, the increasing complexity of HBM stacking, with more dies per stack and ... Read original →

Shifting HBM testing left marks a structural shift in AI chip manufacturing, not just a yield tactic. Technically, TSV defects scale exponentially beyond 4-die stacks, forcing deep integration of DFT and MBiST—Synopsys will dominate test IP standards. MEMS probes must endure extreme thermal stress during wafer-level burn-in, making FormFactor’s thermal solutions critical. Geopolitically, U.S. export controls on advanced packaging tools may delay HBM4 ramp-ups in Taiwan, China, inflating global foundry costs. Teradyne is leveraging its J750 platform to embed IEEE 1500 compliance, while Aehr Test Systems targets wafer-level aging niches. Within 18 months, HBM5 development will pressure JEDEC to fast-track new test specs, pushing test-related capex beyond 12% of total—second only to lithography.