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Shanghai Orient Computing Core Technology has launched the DF1000, a 14-nanometre AI accelerator that uses software-defined computing and 3D-stacked near-memory architecture to reduce reliance on advanced process nodes and high-bandwidth memory, as Sohuand ICsmartreported.

Intel is developing a new memory architecture aimed at challenging the dominance of high-bandwidth memory (HBM), with commercialization targeted for around 2030. Although the path is fraught with ecosystem barriers and compatibility hurdles, Intel's parallel development of Z-angle memory (ZAM) and cross-batch memory (XBM) underscores its determination to re-enter the DRAM market, as it simultaneou

Intel’s XBM patent proposes an HBM alternative that uses backend-transistor DRAM, UCIe chiplet links, and repair logic to reduce packaging costs and complexity.

Tech Industry Manufacturing Semiconductors Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repair to ease AI's memory bottleneck News By Etiido Uko Published 2 days ago The patent was filed 18 months ago, and there's no further indication of ongoing development (Image credit: Intel) Share

As AI models scale to trillions of parameters, conventional memory architectures face mounting capacity and efficiency constraints.