Zhongke Tongliang Unveils Full-Stack Domestic RISC-V Data-Flow Intelligent Computing Products at 2026 CNCC China National Computer Conference - eu.36kr.com

The critical signal here isn't RISC-V—it's "data-flow." Every major Chinese AI chip player (Huawei Ascend, Cambricon, Moore Threads) follows the same playbook: open ISA plus fixed-function accelerators. Data-flow architecture inverts the von Neumann model entirely: execution is triggered by data availability, not sequential instruction fetch. This is architecturally superior for graph-based AI workloads and can theoretically bypass the memory-wall bottleneck that has plagued traditional designs for a decade. The "full-stack" claim is the real differentiator. Graphcore spent eight years building Poplar before commercial viability. If Zhongke Tongliang has a working compiler, runtime, and application framework, that implies three to five years of deep R&D—a moat far deeper than simply taping out a RISC-V core. Competitively, this niche is currently unoccupied domestically. The existential threats are twofold: Huawei pivoting Ascend toward data-flow execution (its ecosystem gravity would crush startups), and SiFive or Tenstorrent shipping data-flow RISC-V variants that capture international developer mindshare. Over the next 12–24 months, the make-or-break metrics are not process node but: (1) whether Alibaba Cloud or Baidu AI Cloud integrates it into production inference clusters, (2) whether RISC-V International standardizes data-flow ISA extensions, and (3) whether domestic EDA tools can handle data-flow topology auto-mapping. Miss any one, and this remains a silicon curiosity.