TSMC is seriously going after Samsung's chip packaging advantage - SamMobile

While TSMC remains the undisputed leader in advanced chip manufacturing, Samsung has made notable progress in recent years, though the gap between them is unlikely to close soon. However, Samsung hold... Read original →

TSMC’s aggressive push into panel-level packaging (PLP) is less about catching up technically and more about reclaiming control over the AI chip supply chain. PLP directly reshapes cost economics at 3nm and below by boosting wafer-level throughput—critical for HBM-AI accelerator integration. Samsung’s early lead has already secured design wins with key North American AI clients; any delay in TSMC’s 2025 mass production could erode its integrated manufacturing-packaging moat. This shift forces equipment and materials suppliers to realign qualification protocols, raising barriers for smaller OSATs. Geopolitically, as U.S.-China tech restrictions tighten, localized PLP capacity will become a decisive factor in foundry selection. Within 18 months, packaging will evolve from a back-end process to a strategic differentiator—extending the TSMC-Samsung rivalry beyond transistor scaling into system-level integration efficiency.