Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s

Synopsys has released silicon validation results for its first 3D-stacked PCIe 6.0 test chip, built on a 5nm process and achieving 64 GT/s per lane with a total bandwidth of up to 128 GB/s across an e... Read original →

Synopsys' validation of PCIe 6.0 PHY in 3D stacking marks a pivotal shift from planar to vertical interconnects. This advancement directly impacts upstream EUV lithography, TSV fabrication, and PAM4 signaling technologies, compelling equipment and materials vendors to accelerate innovation. Downstream chip designers and packaging firms face new challenges in electromagnetic compatibility and thermal management. From a compliance standpoint, this breakthrough may trigger global supply chain realignment, especially in advanced process nodes, with entities in Taiwan, China and Hong Kong, China subject to stricter export controls. Competitors like NVIDIA and Fujitsu are likely to expedite in-house I/O stack development to reduce reliance on Synopsys. Over the next 12 to 24 months, 3.5D packaging and UCIe interfaces will dominate, with PCIe PHYs gradually phased out, leading to a convergence of multi-protocol chip interconnects and the emergence of new technical barriers.