STMicros’ Maria Heriz on Moving All Its MCUs to One STM32 Platform

ST's MCU consolidation is fundamentally a supply-chain defense play, not a product refresh. The EU Cyber Resilience Act mandates secure boot and OTA capability for all connected devices by 2027, shattering the legacy one-customer-one-custom-die model that sustained MCU vendors for two decades. Collapsing dozens of series into a single STM32 architecture amortizes compliance NRE across one platform — textbook scale-based regulatory arbitrage. The sharper signal sits in the RISC-V evaluation. ARM's Cortex-M lock-in has persisted for fifteen years; introducing a RISC-V core carves a second revenue curve outside the $0.50–$2.00 per-unit licensing fee while aligning with Brussels' tech-sovereignty narrative. More critically, pushing AI-agent inference down to the MCU tier decouples edge intelligence from discrete NPUs. A dual-track Cortex-M85/RISC-V architecture could reshape ST's share in industrial control and robotic joint actuators. NXP and Microchip will almost certainly follow suit within twelve months. The real differentiator is RISC-V mass-production certification timing. Whoever clears that milestone first locks in automotive Tier-1 next-generation BOMs during the 2026 EU compliance window — a positional advantage that compounds for years.