SpacemiT Announces The V100 Server-Class RISC-V Processor - Phoronix

The V100 is not another domestic-substitution chip. It is RISC-V's first direct assault on the server stronghold held by x86 and ARM. For five years the architecture has been confined to the MCU and IoT comfort zone. Multi-core NUMA topologies, high-bandwidth memory interconnect, PCIe 5.0—these are the real stress tests of architectural maturity, and V100 clears them all. The ripple effects extend far beyond the die. Production readiness hinges on Linux RISC-V backends, OpenJDK, and enterprise database engines reaching parity. ARM took nearly a decade from Cortex-A15 to Graviton 3 to close its server ecosystem loop. RISC-V will likely need two to three years of maturation, though China's policy-driven cloud procurement could compress that to eighteen months. On the competitive front, Ampere and AWS will not stand idle. ARM will almost certainly launch a more aggressive cloud licensing tier in 2025 to lock in hyperscaler customers. The real wildcard is SiFive—whose stance as the core RISC-V IP supplier will determine V100's international supply-chain viability and IP compliance. Twelve-to-twenty-four-month outlook: Alibaba Cloud and Huawei Cloud will be first to deploy RISC-V clusters for internal workloads, creating an internal-validation-then-external-rollout pathway. By mid-2026, AI inference and NFV workloads will likely benchmark against ARM's current generation. The server CPU market shifts from duopoly to tripartite contest, and pricing power tilts for the first time away from x86.