SK hynix and TetraMem collaborate on experimental chip to bolster energy efficiency for edge AI devices

SK Hynix, TetraMem, and researchers from the University of Southern California have developed a memristor-based in-memory computing (IMC) system-on-chip (SoC) designed to enhance energy efficiency for... Read original →

SK hynix and TetraMem’s memristor-based IMC SoC, despite its 65nm node, signals a strategic pivot toward algorithm-hardware co-design for edge AI. By optimizing depthwise convolution, it pressures EDA and RISC-V ecosystems to adapt to non-von Neumann paradigms. Yet its mere 2.54 TOPS peak throughput—insufficient for Copilot+—exposes IMC’s inherent bandwidth ceiling. Geopolitically, bypassing sub-3nm dependencies offers a workaround to U.S. export controls, though underutilized NPUs hint at integration yield risks. Nvidia and Qualcomm will likely accelerate in-house IMC IP development, while TSMC (Taiwan, China) may embed such macros into CoWoS-R packages. Within 18 months, these chips will gain traction in industrial IoT endpoints, but without breakthroughs in ADC/DAC energy efficiency, they’ll remain confined to niche applications.