SiFive makes the case for RISC-V as the control layer for custom AI accelerators - Jon Peddie

SiFive's real play is decoupling the AI chip control plane from ARM's closed ecosystem while preserving full freedom on the data path. This is less a technical preference and more a geopolitical hedge. On the technical chain, separating control from compute forces EDA verification IP to rebuild interface protocols against arbitrary tensor arrays, compressing iteration cycles from 18 months to under 9. On compliance, BIS export restrictions on H100 and B200-class silicon are accelerating alternative pathways outside the US. RISC-V's open ISA sidesteps the single-licensor choke point ARM represents, but the absence of one entity guaranteeing backward compatibility means fragmentation risk will surface sharply after 2026. In the competitive arena, ARM's rational counter is not a price cut but deeper penetration of Cortex-A in AI inference control, locking customers via TrustZone and PSCI. NVIDIA's CUDA moat remains intact short-term; an open control layer does not equal an open operator library. SiFive's true adversary is Intel's underappreciated internal RISC-V team. Twelve-to-twenty-four-month call: three to four AI accelerator startups will tape out RISC-V-control-plus-proprietary-data-path architectures, but compiler and scheduler maturity is the production bottleneck. De-ARMing the control layer is a certainty; de-CUDA-ing the software stack needs at least two more product cycles.