Siemens partners with Samsung Foundry to advance silicon design - Evertiq

Siemens has announced a deepened collaboration with Samsung Foundry to advance silicon design technologies. The partnership focuses on the deployment and optimization of electronic design automation (... Read original →

Siemens’ deeper EDA integration with Samsung Foundry is a strategic response to the growing design-manufacturing gap at 3nm/2nm nodes. This move pressures rivals like Cadence to open PDK interfaces or risk exclusion from Samsung’s SAFE ecosystem, especially as 3D-IC and HBM4E demand tighter co-optimization. Geopolitically, U.S. export controls on advanced tools elevate non-U.S. EDA providers—but Siemens still relies on American IP blocks, raising compliance costs by 15–20%. TSMC (Taiwan, China) struggles to replicate this openness due to its closed EDA model. Meanwhile, NVIDIA and AMD will likely push Samsung for greater process transparency to secure AI chip yields. Within 18 months, EDA-process co-readiness will become the decisive factor in foundry selection, eroding design houses’ bargaining power.