Samsung Collaborations On 2nm And 3D‑IC Put Investor Focus On Valuation - Yahoo Finance

Samsung Electronics has intensified collaborations with Synopsys and Cadence to advance next-generation chip design and manufacturing processes for its 2nm and 3D-IC technologies. These partnerships f... Read original →

Samsung’s intensified partnerships with Synopsys and Cadence on 2nm and 3D-IC aren’t just technical upgrades—they’re a defensive play against AI chip design complexity spiraling beyond conventional scaling. This triggers a cascade: EDA tools must evolve toward multi-physics simulation, while materials and packaging suppliers scramble to align with heterogeneous integration standards. Geopolitical friction amplifies risk—tightening U.S. export controls on EUV and advanced tools could inflate Samsung’s non-U.S. redundancy costs by 15–20%. TSMC will likely counter with accelerated CoWoS-R capacity and N2P ramp, while Intel pushes Foveros Direct to HPC clients. Over the next 18 months, Samsung’s valuation gap won’t close unless it converts process leadership into customer wins; in an AI market dominated by North American hyperscalers, transistor density matters less than supply chain sovereignty.