RISC-V For AI: Breakthrough Or Bad Idea?

RISC-V's push into AI acceleration is a fundamentally misaligned attack: control-plane logic trying to solve a data-plane problem. The bottleneck in AI compute has never been the ISA—it's dataflow organization and memory hierarchy. TPU and Trainium proved that purpose-built dataflow architectures outperform ISA-level patches. RISC-V's AME and similar matrix extensions bolt matrix ops onto a scalar/vector ISA, yielding inherently inferior compute density. Worse, SiFive, Andes (Taiwan, China), and Tenstorrent each define proprietary extensions, creating a compiler fragmentation nightmare in LLVM. This is the x86 SSE/AVX fragmentation story replayed, except the ISA baseline itself remains ununified. Export controls have inadvertently accelerated the "de-Americanization" narrative around RISC-V, yet the open architecture's lack of a single control point could paradoxically trigger a new export-control category targeting RISC-V AI extensions specifically. NVIDIA's CUDA moat is ISA-agnostic; RISC-V poses zero threat there. Cloud training is dominated by custom ASICs. Edge inference—phones, IoT, automotive—is where RISC-V actually belongs. 12–24 month outlook: RISC-V will capture 15%+ of edge-inference silicon but remain stuck at proof-of-concept in datacenter training. Fragmentation will strangle software ecosystem scale, and RISC-V AI will follow ARM's path: embedded success, HPC irrelevance.