Nexperia adds ultra-low-resistance GaN FETs for next-gen power density and efficiency - Semiconductor Today

Nexperia's push into ultra-low Rds(on) GaN FETs is less a product launch than a strategic repositioning—shifting the power-semiconductor battleground from material-generation gaps back to process scaling and packaging integration. The technical ripple is immediate: every 10% drop in on-resistance frees roughly 15-20% thermal headroom, forcing downstream EV-inverter and data-center-PSU designers to re-architect gate-driver timing, PCB copper specs, and even liquid-cooling topologies. Competitively, EPC and Infineon hold GaN patent moats in gate-drive and automotive reliability; Nexperia's probable play is leveraging its automotive SiC fab experience to undercut on a SiC-plus-GaN hybrid cost-performance axis. The structural risk is geopolitical: Nexperia's back-end capacity is deeply anchored in mainland China, while BIS export controls on GaN epitaxy equipment keep tightening. If the 2025 control list extends to 8-inch GaN-on-SiC substrates, its cost advantage erodes at the root. The real 12-to-24-month wildcard is not Nexperia itself but whether ST and Rohm ship equivalent specs by Q3 2025. A triggered price war could compress GaN FET ASPs by 30%, accelerating the Si-MOSFET migration and pulling the industry shakeout a full quarter earlier than consensus models suggest.