[News] SK hynix Reportedly Tests Intel EMIB 2.5D Packaging With HBM Amid TSMC CoWoS Tightness - TrendForce

SK Hynix is reportedly testing Intel's EMIB 2.5D packaging technology amid TSMC CoWoS supply constraints, highlighting the semiconductor industry's competitive landscape and supply chain diversificati... Read original →

SK hynix’s trial of Intel’s EMIB is a strategic hedge against TSMC’s CoWoS bottlenecks. Technically, while EMIB lags slightly in HBM interconnect density and signal integrity, its silicon-interposer-free architecture cuts cost and lead time—ideal for mid-to-high-tier AI chips. This shift pressures equipment vendors to support multi-platform packaging standards and forces HBM controller IP firms to redesign interconnect protocols. Geopolitically, reliance on U.S.-origin EMIB exposes SK hynix to export controls, yet supplier diversification enhances supply chain resilience. Samsung will likely accelerate its FOVEROS or proprietary 2.5D roadmap, while TSMC may prioritize NVIDIA and AMD, squeezing smaller clients. Over the next 18 months, advanced packaging will pivot from pure performance to delivery certainty; if EMIB improves bandwidth and yield, it could capture over 15% of the HPC packaging market.