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Memory supplies are “only getting tighter,” Micron CEO says - Ars Technica

arstechnica.com 2026-10-02 Ars Technica
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Memory ShortageHBMAI ChipsMicronSamsungDRAMHigh Bandwidth MemoryServer MemorySemiconductor Supply ChainProduction CapacityConsumer MemoryWafer ManufacturingAI Data CenterSuper Cycle
News Summary
The memory supercycle now unfolding is structurally different from prior shortages, driven by sustained AI infrastructure capex rather than speculative hoarding. Micron's CEO and Samsung's EVP have in... Read original →
Industry Analysis
This is not a cycle; it is an irreversible reallocation of the industry's center of gravity. HBM4/4E's hybrid bonding process cuts effective per-wafer yield by 15-20%, while HBM's share of total DRAM capacity climbs from roughly 20% to 30% by 2027. Consumer DDR5 has been demoted to residual demand. Micron's full exit from consumer RAM is a strategic declaration, not a tactical retreat—when AI server memory commands 3-4x the gross margin, wafer capacity will always flow to the highest-value node. The critical risk is temporal: 2028 cleanroom capacity requires 18-24 months to reach full utilization, while model parameter counts double roughly every six months. With 75% of 2027 output already under long-term contracts, the spot market is now a price-discovery mechanism, not a supply source. Samsung will likely push more aggressive hybrid bonding yield targets at HBM4 to reclaim share; SK Hynix may deepen TSV stacks to preserve its trade-ratio edge. Downstream impact is structural, not cyclical: server OEMs secure guaranteed allocation at premium pricing, while PC and mobile OEMs face persistent BOM inflation and configuration downgrades. Unlike the 2018 episode—speculation-driven, cleared in 18 months—this tightness is anchored in secular AI infrastructure capex. Marginal relief, if it comes, is a 2H2028 story at the earliest.
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