Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds - Phoronix

With the upcoming Linux 7.2 kernel release, a significant update is set to enable default support for ESWIN SoC in RISC-V kernel builds. Proposed by Anirudh Srinivasan from Tenstorrent, this change ad... Read original →

Linux 7.2’s default enablement of ESWIN SoC support marks RISC-V’s pivot from experimental validation to mainstream deployment. Technically, this accelerates BSP and driver standardization, lowering integration barriers for SiFive-class IP vendors while pressuring EDA tools to align with open-source workflows. From a compliance standpoint, Tenstorrent’s kernel-level contribution mitigates export control exposure and strengthens supply chain resilience. Arm will likely counter by optimizing Cortex-A licensing for embedded markets and undercutting entry-level IP pricing to curb RISC-V adoption. Within 18 months, the HiFive Premier P550 will solidify as the de facto reference platform, prompting foundries in Taiwan, China and Southeast Asia to prioritize RISC-V-optimized process nodes—catalyzing commercial scale-up in AIoT and edge AI chips.