KYEC warns AI demand is amplifying semiconductor supply-chain risks

Core thesis: The AI test segment is undergoing a "signal contamination" crisis whose systemic risk is severely underpriced by the market. Technical cascade: HBM stacking, CoWoS, and 2nm nodes stretch per-die test cycles by 3-5x. The binding constraint is not ATE hardware—Advantest and Teradyne backlogs already extend into 2026—but test program development. Coverage requirements scale exponentially per generation, making senior test engineers scarcer than wafer capacity itself. Risk assessment: Distorted demand signals cascade inventory-mismatch risk into the test layer. The 2021 memory "bullwhip" is likely to replay: hyperscaler panic-locking amplifies true end-market demand, and if AI inference commercialization lags, test capacity flips from tight to glut within two quarters. Concentration of test capacity in Taiwan, China (KYEC, ASE, UMC) layers geopolitical amplification onto this cyclical risk. Competitive dynamics: TSMC and Samsung are accelerating back-end test internalization, directly compressing independent test-house share. Advantest is locking in HBM test positioning; Teradyne hedges via automotive and industrial. 12-24 month outlook: Expect a price-capacity scissors gap—AI chip test ASPs up 30-50% while non-AI segments face compression. Industry consolidation will follow; smaller test houses face acquisition or exit.