Japanese chipmaker Rapidus to offer lower wafer pricing than TSMC — 2nm class silicon to be priced around $20,000 on 2027 launch

Japanese chipmaker Rapidus plans to challenge TSMC by offering lower wafer pricing, with its 2nm-class silicon priced around $20,000 per wafer upon launch in 2027. While this pricing strategy appears ... Read original →

Rapidus’s $20,000 wafer pricing for 2nm-class nodes isn’t just aggressive—it’s a geopolitical gambit to revive Japan’s semiconductor sovereignty. Technically, its single-fab rapid-turn model may speed up prototyping, but without TSMC’s OIP ecosystem of silicon-proven IPs and EDA co-optimization, customer yield ramp will lag. Geopolitically, U.S.-Japan chip alliances are fueling 'de-risking,' enabling Rapidus to price below cost via state subsidies—a non-market tactic. TSMC will likely counter not with price cuts but by locking in AI/HPC clients with N2X and A16’s superior power efficiency. Samsung and Intel may double down on mature nodes to retain volume customers. Within 18 months, if Rapidus fails to convert its 60+ prospects into long-term contracts, unsustainable EUV operating costs and depreciation will expose its pricing as a short-lived subsidy play, relegating it to regional backup capacity.