Infineon unveils RISC-V-based AURIX platform for SDV and AI systems - New Electronics

Infineon's AURIX pivot from ARM to RISC-V is a structural break in two decades of automotive MCU architecture, not a routine roadmap update. Since 2004, AURIX anchored the ARM Cortex-R ecosystem for global Tier-1s—AUTOSAR, QNX, and ASIL-D certification all built around it. A RISC-V migration forces full-stack revalidation from BSP to middleware. The embedded AI inference core signals a "RISC-V control + NPU" heterogeneous topology, contesting Qualcomm's Snapdragon Ride at the MCU cost tier. SiFive and Andes (Xinwei) gain their first automotive-grade production validation; Bosch and Continental face concentrated software re-engineering costs within 12 months. Compliance: ARM's post-2023 licensing tightening and US EDA export controls make RISC-V's open ISA a natural sovereignty hedge for EU OEMs. Infineon, a pillar of the EU Chips Act, is aligning with Brussels' technological-sovereignty narrative. The risk: no unified ASIL-D standard for RISC-V exists yet—OEM-level fragmentation will slow mass-production timelines. Competitively, NXP and Renesas remain deeply ARM-locked and slow to follow. Chinese MCU players are already RISC-V-native; Infineon's move is simultaneously defensive (blocking Chinese OEMs from bypassing its ecosystem in the SDV era) and offensive (locking global OEMs into open-architecture long-term commitments). 12–24 month outlook: AUTOSAR RISC-V Profile enters standardization votes; Chinese NEV leaders likely first to mass-produce; ARM forced to offer automotive RISC-V-compatible cores to retain customers. The ARM monopoly era in automotive MCUs is ending.