Imec unlocks system-level III-V chiplet integration on Si-CMOS - Evertiq

Imec, a Belgian research center in nanoelectronics and digital technologies, has unlocked system-level integration of III-V chiplets on Si-CMOS. By combining high-density embedded capacitors, a scalab... Read original →

Imec’s breakthrough in system-level III-V chiplet integration on Si-CMOS fundamentally reconfigures the RF front-end stack. By embedding ultra-dense MIMCAPs using high-k AlHfO dielectrics and leveraging laser-assisted bonding, it solves the critical area penalty of passive components at mmWave/sub-THz frequencies—elevating RF silicon interposers to a strategic layer in advanced packaging. This pressures upstream material suppliers to scale high-k oxide production while enabling telecom OEMs to accelerate 5G-Advanced and 6G prototyping. Geopolitically, reduced reliance on GaAs/GaN epitaxial wafers weakens U.S. export controls’ leverage, though laser bonding tools remain restricted under Wassenaar. TSMC will likely counter with accelerated SoIC-RF development, while Intel may fortify its EMIB-based chiplet ecosystem. Within 18 months, expect pilot deployments in AI data-center optical interconnects and LEO satellite terminals, igniting a standards race over high-frequency passive integration.