How US-China tech ties are deepening as RISC-V chips go mainstream - South China Morning Post

RISC-V's shift from niche to volume production is a structural deconstruction of the x86-ARM duopoly. The real chain reaction isn't in silicon—it's in EDA verification flows, compiler ecosystems, and OS adaptation layers where value actually accrues. Linux kernel RISC-V support crossing from experimental to production-grade is compressing software-stack migration costs faster than most models capture, forcing Synopsys and Cadence to recalibrate their verification methodologies. On compliance, the open ISA inherently sidesteps ARM-style licensing friction, but "open specification" does not equal "open implementation." If US export controls pivot from process-node restrictions to microarchitecture-level restrictions, Chinese high-end RISC-V cores will still trip regulatory red lines. Dual-track compliance costs for multinational fabless players will likely climb 15-25%. The most ironic market dynamic: SiFive and T-Head share the same open standard yet compete head-to-head on performance and ecosystem depth. ARM's mobile moat is eroding; Intel's server x86 fortress faces a RISC-V-plus-AI-accelerator pincer. The open standard paradoxically becomes the deepest adhesive in US-China tech interdependence—both sides competing on the same blueprint while decoupling rhetoric dominates headlines. 12-24 month outlook: embedded penetration crosses 25%; the first million-core RISC-V data-center clusters ship. The long-tail effect is structural—once RISC-V cements its position as a credible third pole, x86 and ARM IP pricing power gets structurally diluted, and the global semiconductor licensing market's power map gets redrawn.