HBM capacity shift sends DDR4 contract prices rising faster than DDR5

This is not a cyclical wobble—it is a structural fracture in the DRAM market. HBM's 3D stacking (TSV + hybrid bonding) consumes 3-4x the wafer area per effective bit versus planar DDR5. When Samsung, SK Hynix, and Micron divert 15-20% of their 1a/1b nm lines to HBM3E, the arithmetic is punishing: every HBM wafer pulled from the line permanently erases 2-3 DDR4 wafers of output. The DDR4-over-DDR5 pricing inversion is the most dangerous signal in this cycle. A "legacy" node has become the scarcer asset. The 2018-19 NAND shortage saw enterprise SSDs outprice consumer products on similar logic, but DDR4's demand is far more inelastic—AEC-Q100 automotive, industrial controllers, and 5G base stations cannot migrate overnight. Strategically, CXMT and Nanya (Taiwan, China) are positioned to absorb the DDR4 "orphan market" as the Big Three chase HBM contracts with NVIDIA and AMD. The HBM arms race is a zero-sum game for wafer capacity. I expect a 12-24 month window where DDR4 commands a 20-35% contract premium over DDR5. This is not a correction awaiting mean-reversion. It is a structural anomaly that will persist until HBM4 volume ramps displace the capacity constraint—likely no earlier than 2027.