EU DARE Project Is Scrambling to Replace Codasip

The European High-Performance Computing Joint Undertaking (EuroHPC JU) and the Digital Autonomy with RISC-V in Europe (DARE) consortium are grappling with strategic realignment by Codasip, a key partn... Read original →

Codasip’s strategic pivot away from low-end RISC-V cores exposes the fragility of Europe’s semiconductor coordination model. While its shift toward CHERI-based cyber-resilient architectures aligns with global security-by-design trends, it forces DARE to urgently re-engineer GPP chiplet interfaces and vector accelerator integration, delaying EuroHPC deployment and straining Siemens EDA toolchain compatibility. On the compliance front, U.S. acquisition of Codasip’s divested assets may trigger EU Chips Act foreign investment screening, inflating supply chain validation costs for alternatives. Competitors like Semidynamics and OpenChip are poised to capture custom RISC-V IP market share, while GUC—backed by TSMC—could accelerate European chiplet packaging services. Without streamlined SGA1 fund disbursement and a technical ‘circuit-breaker’ mechanism within 18 months, similar disruptions will recur in AI accelerators and automotive chips, turning Europe’s tech sovereignty ambition into hollow rhetoric.