Energy efficient compute is most important attribute for customers, TSMC claims - Data Center Dynamics

At TSMC's Technology Symposium in Amsterdam on May 28, Kevin Zhang, Deputy Co-CEO and SVP, stated that customers are now prioritizing energy efficiency over other performance metrics when it comes to ... Read original →

TSMC’s (Taiwan, China) pivot to energy efficiency over raw performance signals a new era of 'compute-per-watt' competition. Technologically, the reliance on EUV layers and Super Power Rail in 3nm/N2U nodes forces EDA, packaging, and thermal solutions to co-evolve; integrated photonics—though nascent—is now critical to bypass copper interconnect limits. Regulatory risks are rising: the EU Chips Act and U.S. IRA incentivize low-carbon fabs, exposing high-energy facilities to carbon tariffs and pressuring TSMC’s Arizona and European expansions. Samsung may accelerate GAA transistor ramp-up to capture HPC sockets, while Intel could leverage Intel 18A with Microsoft Azure to reframe its efficiency narrative. Over the next 12–24 months, AI chip benchmarks will shift from peak TFLOPS to sustained efficiency ratios, demanding tighter GPU-foundry co-design. If NVIDIA fails to integrate photonic I/O at the 1.2nm node, its pricing power in hyperscale data centers will erode.