Chinese chipmakers roll out new RISC-V server CPUs for AI demand - Global Times

The mass deployment of RISC-V server CPUs is a structural decoupling of China's compute infrastructure from the x86/ARM licensing duopoly. The real bottleneck is not the ISA—it is the maturity of multi-core cache coherence, hypervisor extensions, and vector AI acceleration in the software stack. This determines whether distributed training runs reliably within 12 months. Upstream, EDA toolchains and IP licensing (SiFive, Andes) capture early value, but SMIC's sub-7nm yield remains the physical ceiling. On compliance, the open architecture sidesteps BIS export controls on ISA licensing, yet EUV lithography and advanced manufacturing remain hard constraints—a "architectural freedom, manufacturing captivity" asymmetry that forces enterprises to reprice supply-chain risk from "can we design" to "can we produce." Strategically, AMD will likely accelerate Zen5 inference optimization to defend x86 moats; ARM may cut server licensing fees to stem share loss. Alibaba Cloud and Huawei Cloud become first-movers, spinning up a de facto "China RISC-V ecosystem flywheel." 12-24 month outlook: AI inference workloads go live first; training needs 2-3 more years of software maturation. The global RISC-V ecosystem will fracture geographically—China dominates server, the West dominates embedded. That bifurcation matters more than any single chip.