Cadence strikes new partnership with Samsung Foundry to deliver 2nm platform for AI chips - My Everyday Tech

Cadence and Samsung Foundry have announced a multi-year collaboration to develop a full portfolio of Memory and Interface IP certified for Samsung's second-generation 2nm process technology. The platf... Read original →

Samsung Foundry’s deep integration with Cadence at the 2nm node isn’t just a process upgrade—it forces a systemic shift across the semiconductor stack. EDA workflows now co-evolve with 3D packaging, compelling IP vendors to align with AI-driven optimization engines like Cerebrus, while customers such as Ambarella slash design cycles via GPU-accelerated verification. Geopolitically, reliance on U.S.-controlled EUV tools or CUDA-X creates compliance friction for non-U.S. clients, accelerating supply chain fragmentation. TSMC will likely counter with N2P plus enhanced CoWoS, and Synopsys may fast-track DSO.ai integration into its 3DIC flow. Within 18 months, access to this intelligent design infrastructure will separate AI chip leaders from laggards—those locked out face irreversible PPA and time-to-market deficits.