Cadence, Samsung expand 2nm IP and design flows - Engineering.com

Cadence and Samsung Foundry have expanded their collaboration to support second-generation 2nm process design with enhanced memory and interface IP, including SerDes, PCIe, UCIe, and NVLink-C2C. This ... Read original →

Samsung and Cadence’s expanded 2nm collaboration is a direct response to the AI chip arms race. Technically, integrating high-speed interconnect IPs like SerDes and NVLink-C2C forces a full-stack EDA re-architecture—especially in 3D IC and power integrity, where Voltus-Tempus co-optimization dictates yield. On compliance, tightening U.S. export controls on advanced tools raise Samsung’s risk of delayed ramp if reliant on non-U.S. EUV support; Cadence’s CUDA-X libraries also face potential ITAR constraints. TSMC will likely accelerate A16/A14 nodes with CoWoS-R integration to counter Samsung’s UCIe lead, while Synopsys leverages NVIDIA’s GB200 NVL72 to push its 3DIC Compiler. Within 18 months, 2nm design platforms will become the key binding mechanism between AI chipmakers and foundries—with edge AI players like Ambarella testing real-world PPA gains first.