Automotive Tech Forum: The Current State of Sic in EV Design and How It’s Evolving

The 800V architecture's shift from premium option to platform default is fundamentally a resonance between SiC cost curves and vehicle electrical topology. The chain reaction has already penetrated beyond the device layer: 8-inch substrate ramp timing now gates 1200V MOSFET supply elasticity through 2026, while gate-driver IC and dual-side cooling packaging iteration windows compress to under 18 months. On the supply side, Wolfspeed's financial restructuring and STMicro's capacity ramp create a partial hedge, yet Chinese device makers scaling 650V-1200V output are pushing annual ASP erosion from roughly 15% toward 25%+. Compliance-wise, EU battery regulation mineral traceability layered with IRA entity-of-concern definitions imposes a compliance premium across the substrate-epitaxy-device stack, likely eroding 3 to 5 percentage points of gross margin for mid-tier IDM players by 2025. The competitive axis—BYD-style vertical integration versus Infineon and ROHM horizontal supply—will resolve by 2026. The 12-to-24-month tail to watch is not 800V itself but the SiC-plus-GaN hybrid architecture infiltrating OBC and DC-DC stages. This will restructure the power-semiconductor BOM and materially dilute pure-SiC TCO advantages before 2027.