ASE expects packaging and testing margins to stay above 30%

ASE anchoring OSAT margins above 30% is not a forecast—it is a declaration that packaging has exited the commodity tier of the semiconductor value chain. AI-driven 2.5D/3D integration (CoWoS, SoIC) has made yield at the packaging stage the true throttle on GPU and ASIC shipment cadence. This re-prices the entire upstream: ABF substrates, underfill chemistries, and bonding equipment now face a customer that behaves like a systems integrator, not a toll manufacturer. The compliance overhang is non-trivial. ASE's mainland China capacity exposure collides with a US export-control regime progressively extending from lithography into advanced bonding and test. Any tightening in 2025-26 forces capex reallocation toward Southeast Asia and Taiwan, China, where near-term depreciation will compress the very margin expansion ASE is projecting. The competitive threat is not Amkor or SPIL. It is TSMC internalizing CoWoS as a quasi-foundry service and pricing packaging with wafer-fab economics. ASE's counter is breadth: multi-client, multi-technology-route flexibility, with a likely 2026 window to lock in proprietary HBM and CPO process IP. Over the next 12-24 months, if AI capex holds its current slope, the 2027 advanced-packaging supply gap of 15-20% makes 30% margins a monetization of scarcity, not optimism. But once the 2028 capacity wave lands, that premium mean-reverts. ASE's durable moat is not equipment—it is the depth of customer process lock-in.