Analysis-Huawei bets on speed over shrinking transistors to sidestep US chip sanctions - WTVB

Facing U.S. sanctions that block access to ASML's most advanced EUV lithography machines, Huawei has proposed a new chip design principle focused on increasing signal transmission speed rather than sh... Read original →

Huawei’s pivot to LogicFolding and the Tau Scaling Law is a tactical workaround against EUV denial, not a Moore’s Law successor. It pressures EDA vendors like Synopsys to overhaul 3D logic verification flows and elevates advanced packaging—where TSMC (Taiwan, China) and Samsung already lead. Without access to high-yield 3D integration fabs, Huawei’s architectural gains risk remaining lab curiosities. The claimed 41% power efficiency boost in its Kirin chip means little without volume validation; thermal density and yield volatility could erode credibility. NVIDIA will likely double down on chiplet ecosystems, locking CoWoS capacity with TSMC to widen its AI lead. Over the next 18 months, unless mainland China cracks hybrid bonding and thermal bottlenecks, such design-centric workarounds won’t shift the global semiconductor power balance.