Analysis-Huawei bets on speed over shrinking transistors to sidestep US chip sanctions - WKZO

Facing U.S. sanctions that block access to ASML's most advanced EUV lithography machines, Huawei has proposed a new chip design principle focused on improving signal transmission speed rather than shr... Read original →

Huawei’s pivot from transistor scaling to LogicFolding and the Tau Scaling Law is a tactical bypass of EUV denial, not a Moore’s Law successor. This shift pressures EDA vendors like Synopsys and Cadence to overhaul timing-centric design flows for 3D-stacked logic—or risk losing relevance in high-end SoC development. For SMIC and other mainland foundries, it reduces lithography dependency but amplifies thermal and yield risks, while U.S. export controls may soon target advanced packaging tools. NVIDIA and Samsung are likely to accelerate Chiplet standardization to lock in architectural dominance. If Huawei’s Kirin chip delivers its claimed 13% performance gain within 12–18 months, the industry could pivot from area efficiency to system-level latency as the new scaling metric; if not, it reveals a critical gap in China’s IP-manufacturing co-optimization capability.