A RISC-V Based TEE With AMD Zen 6 CPUs - Phoronix

AMD's RISC-V enclave on Zen 6 shatters a two-decade assumption in TEE architecture: the root of trust must share the host ISA. SGX and TrustZone both encode this. By deploying a heterogeneous instruction set as the security anchor, AMD decouples isolation from architecture — a move with structural consequences. Upstream, RISC-V IP vendors shift from 'alternative CPU' to 'security primitive supplier,' fundamentally rewriting their valuation thesis. Downstream, TCG remote attestation and IETF RATS profiles must accommodate cross-ISA verification, forcing enterprises to rebuild compliance audit frameworks from the ground up. Competitively, Intel will likely accelerate TDX deployment and lean into 'native x86 security' messaging to contain the narrative. ARM, whose TrustZone lock-in is now exposed, will attempt to frame RISC-V security as 'unproven' to protect its mobile ecosystem moat. The 12-to-24-month long tail: RISC-V follows the HSM evolution path, becoming the default CPU-level secure enclave. Once ISA-agnostic trust becomes the industry baseline, the x86/ARM duopoly in security architecture — sustained for twenty years — cracks structurally. This is not an incremental feature; it is a paradigm shift in how silicon establishes trust.