2025 RISC-V China Summit: RayCore Highlight D35 On-Site Showcase – RISC-V x Data Stream, Breakthrough Innovation for Domestic AI Chips - 36Kr

The D35's real differentiator isn't RISC-V—over a dozen Chinese firms already ship open-ISA AI accelerators. The structural break is the data-stream architecture dismantling the von Neumann bottleneck. Traditional AI chips burn over 70% of power on data movement; decoupling compute from data paths yields a theoretical 3-to-5x efficiency gain. With advanced nodes constrained, architecture innovation becomes the second path around process restrictions, echoing Huawei's 2018 Ascend strategy of outperforming Turing at 16nm via the Da Vinci design. Upstream, data-stream scheduling demands new EDA timing-convergence tooling, creating incremental demand for Empyrean and Primarius. Compiler stacks like CANN and Triton face fundamental rewrites, exposing the software ecosystem as the most fragile moat. Competitively, Cambricon and Biren remain on SIMD trajectories. D35, if it clears production validation, carves out a distinct position in edge inference and automotive ADAS. AMD's SiFive-backed RISC-V datacenter roadmap could collide head-on by 2026. The 12-to-24-month litmus test: can D35 land at least two tier-1 OEM design wins? The graveyard for RISC-V AI silicon isn't the die—it's operator library coverage and framework compatibility. The day the software stack matures is the day China's AI inference chip market undergoes its first real consolidation.