18V – 200V GaN devices deliver RDS(on) down to 0.32mΩ in compact - Electronic Products & Technology

The 0.32mΩ figure is not a GaN story—it is a 48V bus architecture story. At 30kW+ per AI rack, every 0.1% PSU efficiency gain translates to multi-million-dollar annual power cost deltas at fleet scale. This is a procurement inflection point, not a lab curiosity. Technical cascade: Sub-0.5mΩ at 18V while retaining 200V blocking implies structural changes in gate stack or channel engineering. The compact-package constraint shifts the bottleneck from die to thermal impedance, creating a two-quarter pull-through on SiC substrates and flip-chip interconnects in the packaging supply chain. Risk vector: Epi-wafer supply remains dangerously concentrated among Piersol, IQE, and Sumitomo. Any tightening on MOCVD equipment or substrate export controls hits non-domestic fabs within two quarters. Domestic players in China and Taiwan, China are closing the gap but have not matched defect-density control at volume. Competitive read: Navitas and EPC will compress their 2025 roadmaps. Infineon's CoolGaN margin in the 48V-75V band faces direct pressure. The real disruption vector is NVIDIA's 800V DC architecture—sub-0.5mΩ GaN shifts from premium option to architectural mandate. 12-24 month call: By mid-2026, the 48V data center standard flips from "GaN optional" to "GaN default." The long-tail lands in automotive: 800V EV platforms push GaN into OBC and DC-DC as silicon's thermal ceiling becomes the binding constraint.