The AI chip race has hit a power wall. With NVIDIA’s H100 GPUs consuming nearly 700 watts and the new Blackwell B200 surpassing 1,000 watts per module, traditional horizontal power delivery architectures in data centers are rapidly becoming obsolete. At Computex 2024 in Taipei, this issue moved center stage: vertical power delivery (VPD) and miniaturized power modules emerged as industry imperatives. This shift is not merely a technical upgrade—it is reconfiguring the semiconductor value chain. NVIDIA defines compute demands, TSMC enables advanced packaging integration, and Texas Instruments (TI) is quietly securing a strategic foothold in next-generation power infrastructure.
NVIDIA is not passively reacting to power constraints. Its Blackwell platform employs a dual-die design that boosts computational density but pushes power delivery complexity to its limits. To sustain performance-per-watt gains, NVIDIA is collaborating deeply with TSMC to integrate power management units directly into CoWoS advanced packaging. This “compute-packaging-power” triad transforms NVIDIA from a GPU vendor into a system architect. I judge that within two years, NVIDIA will allocate at least 30% of its R&D resources to co-designing power integrity and thermal management—a strategic necessity to preserve its AI dominance.
TSMC’s role extends far beyond contract manufacturing. Its CoWoS-L and SoIC 3D integration technologies are becoming critical enablers of VPD. By relocating power rails from PCB layers into silicon interposers or even within dies, TSMC drastically shortens current paths, reducing IR drop and parasitic losses. According to its 2025 technology roadmap, TSMC plans to introduce backside power delivery at the 2nm node, further decoupling signal and power routing. This evolution means advanced packaging is no longer just about interconnects—it is becoming the core of power architecture. Foundry capabilities in Taiwan, China, thus shift from “capacity output” to “architectural authority,” heightening both geopolitical risk and technological indispensability.
Yet the real wildcard is Texas Instruments. As the world’s largest analog chipmaker, TI has long dominated the server VRM (voltage regulator module) market. Facing AI workloads’ extreme demands for transient response, efficiency, and size, TI is miniaturizing its GaN (gallium nitride) and advanced DC-DC converter technologies and promoting the concept of “chiplet-level power.” For instance, its latest 60A smart power stage module measures just 5mm × 6mm and can be embedded directly into substrates or packages. Though individually low-value, these components achieve near-ubiquitous system-level penetration. If VPD becomes standard, TI could deploy dozens of power management ICs per AI accelerator card—building an invisible moat.
The relationship among these three is not purely collaborative. NVIDIA seeks highly customized power solutions to maximize performance, TSMC favors standardized packaging interfaces to improve yields, and TI must balance universality against client-specific requirements. This tension is already visible in the Blackwell supply chain: initial production bottlenecks stemmed partly from power module delays, not GPU availability. More profoundly, if power delivery becomes the new bottleneck in AI hardware, companies mastering high-efficiency, high-density power—whether legacy analog giants like TI or emerging GaN startups—could gain unprecedented pricing power.
Notably, U.S. support for domestic power semiconductor manufacturing under the CHIPS and Science Act remains inadequate. High-end VRMs rely heavily on Asian supply chains, particularly in Taiwan, China, and Japan. A geopolitical disruption could leave AI data centers stranded with chips but no power—a scenario prompting NVIDIA and others to evaluate North American alternatives. TI’s 300mm analog wafer fab in Utah is thus undergoing strategic reassessment.
Power, once seen as a mere enabler, is now the frontier of AI hardware innovation. NVIDIA sets the compute boundary, TSMC constructs the physical vessel, and Texas Instruments ensures energy arrives precisely where needed—collectively defining the foundational logic of next-generation AI infrastructure. But one critical question remains unresolved: as compute scaling slows, will power efficiency become the primary battleground for AI chips? If so, victory may belong not to the most powerful engine, but to the most efficient energy steward.