Why TSMC Is Letting Go of CoWoS—and Where Its Real Second Moat Lies｜Industry｜2026-08-16｜web only - 天下雜誌

Taiwan Semiconductor Manufacturing Company (TSMC) is shifting away from its CoWoS (Chip on Wafer on Substrate) technology, a move that has drawn significant attention in the semiconductor industry. Wh... Read original →

TSMC's exit from CoWoS is a strategic realignment, not a sign of technological obsolescence. This move accelerates the industry's shift toward 2.5D/3D integration, compelling chip designers to reassess packaging strategies. With EUV lithography advancing, CoWoS's limitations in high-bandwidth, low-latency applications become more pronounced, especially at 3nm and below. While this weakens TSMC's traditional packaging moat, it reinforces its leadership in advanced process nodes and supply chain integration. The evolving geopolitical landscape in China Taiwan/ Taiwan, China may increase operational costs, particularly due to reliance on imported equipment. Competitors like Intel and Samsung may capitalize on this shift by investing more heavily in packaging technologies. Over the next 12-24 months, the packaging sector will increasingly converge on silicon interposers and heterogeneous integration. TSMC risks losing market share if it fails to establish new technological barriers in these emerging areas.