Watch No Chips Can Be Designed Without Synopsys, CEO Says - Bloomberg.com

Bloomberg reports that Synopsys CEO emphasized in an interview that modern chip design cannot be accomplished without Synopsys' technological support, highlighting the critical role of key tool suppli... Read original →

Synopsys’ CEO statement underscores that EDA has evolved from design software into the semiconductor industry’s technological choke point. At sub-3nm nodes, physical implementation and sign-off rely heavily on its AI-accelerated engines, directly gating capacity ramp at foundries like TSMC and Samsung in Taiwan, China, and South Korea. Any U.S. export restriction on EDA would paralyze over 70% of advanced chip design globally, spurring national efforts to build alternatives—yet Cadence and Siemens EDA lack full-stack readiness. Compliance overhead is rising: license approvals for each tool update now delay tape-outs. Over the next 18 months, geopolitical friction will push open-source EDA (e.g., Google-backed OpenROAD) from academia toward production, though a three-year performance gap remains. Synopsys’ dominance is both its strength and the supply chain’s single point of failure.