Wafer-Scale vs. Chiplet: Solving the Data Movement Bottleneck in HPC - News and Statistics - IndexBox

In high-performance computing, data transmission bottlenecks have become a critical constraint limiting chip performance advancement. As Moore's Law approaches physical limits, the industry is explori... Read original →

The data movement bottleneck is forcing HPC architectures to shift from monolithic dies to heterogeneous integration. TSMC’s (Taiwan, China) wafer-scale CoWoS and NVIDIA’s chiplet strategy appear competitive but are functionally complementary: the former leverages 3nm EUV for extreme bandwidth, while the latter uses UCIe to decouple performance from a single advanced node. This accelerates demand for domestic alternatives in advanced packaging tools, silicon interposers, and high-speed SerDes IP. Tightening U.S. export controls on advanced packaging raise supply chain costs for non-U.S. AI chipmakers. Intel and AMD will deepen chiplet ecosystems to counter NVIDIA’s vertical stack, while Samsung pushes HBM4-integrated I-Cube for data center wins. Over the next 18 months, chiplets will dominate AI training clusters, while wafer-scale remains niche; the real race is to establish cross-process, cross-border chiplet quality certification frameworks.