Vertical Semiconductor awarded $73m in CHIPS Act funding to support vGaN transistor development - Data Center Dynamics

The $73M CHIPS allocation to Vertical Semiconductor is not a research grant—it is a geopolitical anchor. By funding vertical-gate GaN specifically, Washington is betting the next power-semiconductor paradigm shift lands on American soil rather than in St. Gallen or Hsinchu. Technically, vGaN's vertical current path collapses the switching-frequency-versus-conduction-loss trade-off that has defined lateral GaN and SiC MOSFETs for a decade. If Vertical reaches volume production, Infineon's and ST's 650V-plus SiC pricing power erodes within two product cycles. Upstream, GaN epitaxy suppliers face a customer-mix reset as design wins migrate. The compliance tail is the real cost. CHIPS strings—domestic fab requirements, annual technology audits, restrictions on certain cross-border IP flows—effectively tax any player still serving restricted markets, accelerating bifurcation of the global power-semiconductor supply chain into two non-interoperable pools. Competitively, Navitas and EPC will compress their vertical-gate roadmaps within twelve months, likely through co-development deals with equipment makers to close Vertical's head start. The 12–24-month tail: once AI data-center rack density crosses 30 kW, vGaN becomes the default for PSU and DC-DC stages. First-to-volume locks in the next generation of hyperscaler power architecture.