TSMC working on cost-reducing advanced packaging process, says analyst - Mezha

Analyst Mezha reports that TSMC is actively developing cost-reducing advanced packaging processes, highlighting the semiconductor industry's ongoing efforts to address rising manufacturing costs and c... Read original →

TSMC’s push to cut costs in advanced packaging is a strategic necessity amid soaring EUV expenses at 3nm and below. This move pressures upstream material suppliers—like those of ABF substrates and temporary bonding adhesives—to accelerate innovation, while forcing downstream system designers to rethink chiplet integration architectures. With U.S. and EU subsidies prioritizing local wafer fabs, packaging has emerged as a geopolitically resilient yet high-value moat, enhancing TSMC’s global delivery flexibility despite constraints on non-Taiwan, China capacity. Facing Intel’s EMIB and Samsung’s I-Cube, TSMC leverages platforms like CoWoS-L to widen its performance-cost gap, compelling rivals into yield-versus-economics trade-offs. If packaging costs drop over 20% within 18 months, it will catalyze a design paradigm shift in AI accelerators and HPC, finally making chiplet-based economics scalable.