TSMC weighs making memory chips at Nvidia’s request - Tech in Asia

TSMC's move is not "making memory" in the DRAM sense — it is collapsing the 40-year wall between logic foundry and memory integration by embedding HBM stacks directly into CoWoS/SoIC packages. Nvidia's request exposes the real AI bottleneck: bandwidth, not FLOPS. The fix requires the foundry to own the memory-interconnect IP itself. Technical ripple: SoIC-X stacking cuts interconnect latency 40%+ versus discrete HBM modules. Upstream, SK Hynix and Samsung must reposition at the packaging layer or lose architectural relevance. Downstream, Nvidia locks a single-source supply chain for Rubin-class accelerators. Compliance gray zone: US BIS export controls on advanced packaging create a classification loophole — if memory integration is filed as "packaging" rather than "memory manufacturing," certain restrictions are sidestepped. But this concentrates AI's critical supply chain in Taiwan, China, amplifying geopolitical leverage. Competitive response: Samsung accelerates its in-house foundry-plus-memory vertical stack. SK Hynix will attempt to reduce TSMC to a pure packaging subcontractor. Micron, locked out of the ecosystem, bets everything on HBM4 self-sufficiency. 24-month call: "memory" as a standalone product category is dying. The unit of value becomes the compute-memory co-designed package. TSMC's margin center of gravity shifts from logic nodes to packaging IP. Nvidia's moat deepens not through silicon design alone, but through structural supply-chain lock-in that no competitor can replicate without rebuilding the entire packaging stack.