TSMC Weighs Making Advanced Memory Chips to Capture More AI Spending - The Information

TSMC's potential entry into advanced memory fabrication is not diversification—it is a structural seizure of HBM architecture leverage from Samsung and SK Hynix. When memory dies and logic dies are co-integrated within a single CoWoS substrate, interconnect latency shifts from a design constraint to a manufacturing variable. The bandwidth bottleneck is no longer solved by stacking more layers; it is solved by shortening the physical path. Downstream, bonding-tool vendors (BESI, ASMPT) face restructured order books, and DRAM's commodity pricing model begins to fracture as memory dies become custom-optimized for specific AI accelerators. Samsung will likely anchor its defense on 2nm GAA for HBM4, but SK Hynix and Micron face a binary: cede manufacturing leverage to TSMC or accept a 12-month-plus technology gap. The 12-to-24-month tail effect: AI chip design paradigms shift from compute-plus-attached-memory to compute-memory co-packaged systems. TSMC's role mutates from pure foundry to AI system architect. The scarce resource stops being transistor density and becomes heterogeneous-integration yield and package-level thermal management.