TSMC Weighs 20% CoWoS Price Hike as AI Packaging Hits Capacity Wall - news.lavx.hu

A 20% CoWoS price adjustment is not routine capacity pricing—it marks the moment advanced packaging transitions from a back-end cost center to the primary value anchor in the AI silicon stack. The technical ripple is structural: with HBM stacks already consuming over 35% of an accelerator's BOM, a two-digit packaging surcharge shaves 5-8 points off gross margins for NVIDIA, AMD, and custom ASIC players. More critically, when packaging cost approaches wafer-fab cost, the ROI inflection for chiplet heterogeneous integration and SoIC hybrid bonding accelerates. Samsung and Intel's HBM4 packaging window may compress from 2027 to 2026. Strategically, TSMC holds pricing power today, but customers will hedge. Broadcom and Marvell are likely to accelerate second-source packaging with ASE and Samsung. ABF substrate suppliers in Taiwan, China, and bonding equipment makers like ASMPT and BESI capture the margin upside. The 12-24 month tail effect is not about price—it is about scarcity redefinition. Packaging capacity, not GPU die output, becomes the binding constraint on AI compute. Hyperscaler capex logic shifts from buying chips to securing packaging slots. TSMC's CoWoS monthly output (~35K wafers) becomes the industry's most critical KPI, surpassing even B200 shipment numbers.